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CY7C344B
32-Macrocell MAX(R) EPLD
Features
* High-performance, high-density replacement for TTL, 74HC, and custom logic * 32 macrocells, 64 expander product terms in one LAB * 8 dedicated inputs, 16 I/O pins * Advanced 0.65-micron CMOS EPROM technology to increase performance * 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344B LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 "buried" registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344B makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial "glue" logic, without using multiple chips. This architectural flexibility allows the CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344B represents the
Logic Block Diagram [1]
15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21)
Pin Configurations
HLCC Top View
I/O I/O I/O VCC GND I/O I/O 4 3 2 1 28 27 26 I/O I/O I O C O N T R O L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3(10) 4(11) 5(12) 6(13) 9(16) 10(17) 11(18) 12(19) 17(24) 18(25) 19(26) 20(27) 23(2) 24(3) 25(4) 26(5) INPUT INPUT/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT INPUT I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT C344B-3 I/O INPUT INPUT INPUT INPUT/CLK I/O I/O 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O INPUT INPUT INPUT INPUT I/O 12 13 14 1516 1718 I/O I/O V CC GND I/O I/O I/O
INPUT/CLK 2(9)
MACROCELL 2 MACROCELL 4 MACROCELL 6 MACROCELL 8 MACROCELL 10 MACROCELL 12 MACROCELL 14 MACROCELL 16 MACROCELL 18 MACROCELL 20 MACROCELL 22 MACROCELL 24 MACROCELL 26 MACROCELL 28 MACROCELL 30 MACROCELL 32 B U S G L O B A L
MACROCELL 1 MACROCELL 3 MACROCELL 5 MACROCELL 7 MACROCELL 9 MACROCELL 11 MACROCELL 13 MACROCELL 15 MACROCELL 17 MACROCELL 19 MACROCELL 21 MACROCELL 23 MACROCELL 25 MACROCELL 27 MACROCELL 29 MACROCELL 31
C344B-2
CerDIP Top View
64 EXPANDER PRODUCT TERM ARRAY
32
C344B-1
Selection Guide
7C344B-15 Maximum Access Time (ns)
Note: 1. Number in () refers to J-leaded packages.
7C344B-20 20
7C344B-25 25
15
MAX is a registered trademark of Altera Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 8, 1999
CY7C344B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +135C Ambient Temperature with Power Applied ..............................................-65C to +135C Maximum Junction Temperature (Under Bias)............. 150C Supply Voltage to Ground Potential[2] ............ -2.0V to +7.0V DC Output Current, per Pin[2] ...................-25 mA to +25 mA DC Input Voltage[2] .........................................-2.0V to +7.0V
Operating Range
Range Commercial Industrial Ambient Temperature -0C to +70C -40C to +85C VCC 5V 5% 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VCC VOH VOL VIH VIL IIX IOZ tR tF Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Recommended Input Rise Time Recommended Input Fall Time GND VIN VCC VO = VCC or GND Test Conditions Maximum VCC rise time is 10 ms IOH = -4.0 mA DC[3] IOL = 8 mA DC
[3]
Min. 4.75(4.5) 2.4
Max. 5.25(5.5) 0.45
Unit V V V V V A A ns ns
2.0 -0.3 -10 -40
VCC+0.3 0.8 +10 +40 100 100
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 12 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 50 pF INCLUDING JIGAND SCOPE Equivalent to: R2 250 R1 464 5V OUTPUT 5 pF R2 250 R1 464 ALL INPUT PULSES 3.0V GND 6 ns 90% 10% tf 90% 10% 6 ns
tR (a) (b)
C344B-5
tF
C344B-6
THEVENIN EQUIVALENT (commercial) 163 OUTPUT 1.75V
C344B-7
Notes: 2. Minimum DC input is -0.3V. During transactions, the inputs may undershoot to -2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
2
CY7C344B
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344B contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND (VIN or VOUT) V CC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled.
Typical ICC vs. fMAX
240
ICC ACTIVE (mA) Typ.
180
VCC =5.0V Room Temp.
120
60
0 100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz C344B-8
MAXIMUM FREQUENCY
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. When calculating synchronous frequencies, use tSU if all inputs are on the input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tSU) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions.
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
250 IOL 200 150 100 IOH 50 VCC =5.0V Room Temp.
0
1
2
3
4
5
C344B-9
VO OUTPUT VOLTAGE (V)
3
CY7C344B
EXPANDER DELAY t EXP LOGIC ARRAY CONTROLDELAY tCLR tLAC tPRE INPUT DELAY tIN LOGIC ARRAY tRSU DELAY tRH tLAD SYSTEM CLOCK DELAYtICS I/O I/O DELAY tIO CLOCK DELAY tIC
REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX
INPUT
I/O
FEEDBACK DELAY tFD
C344B-10
Figure 1. CY7C344B Timing Model
External Synchronous Switching Characteristics Over Operating Range
7C344B-15 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT tODH fCNT Description Dedicated Input to Combinatorial Output Delay I/O Input to Combinatorial Output Delay[4] Global Clock Set-up Time Synchronous Clock Input to Output Delay Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Frequency
[6] [5] [4] [4]
7C344B-20 Min. Max. 20 20 12
7C344B-25 Min. Max. 25 25 15 15 0 8 8 Unit ns ns ns ns ns ns ns 62.5 20 1 50 MHz ns ns MHz
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 1 76.9 0 6 6 83.3 9
Max. 15 15 10
12 0 7 7 71.4
Input Hold Time from Synchronous Clock Input
13 1 62.5
16
Notes: 4. C1 = 35 pF 5. The f MAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a 32-bit counter programmed into each LAB.
4
CY7C344B
External Asynchronous Switching Characteristics Over Operating Range
7C344B-15 Parameter tACO1 tAS1 tAH tAWH tAWL tACNT fACNT Description Asynchronous Clock Input to Output Delay[4] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time Asynchronous Clock Input LOW Time
[7] [7]
7C344B-20 Min. 6 6 7 9 Max. 18
7C344B-25 Min. 8 8 9 11 Max. 22 Unit ns ns ns ns ns 20 50 ns MHz
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 76.9 5 5 6 7
Max. 15
Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency[6]
13 62.5
16
Typical Internal Switching Characteristics Over Operating Range
7C344B-15 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tIC tICS tFD tPRE tCLR Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Disable Delay
[4]
7C344B-20 Min. Max. 5 5 10 10 4 4 7 7 4 8
7C344B-25 Min. Max. 7 7 15 13 4 4 7 7 5 10 Unit ns ns ns ns ns ns ns ns ns ns 1 1 1 10 3 1 9 9 ns ns ns ns ns ns ns ns
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l /Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 4 5
Max. 3 3 8 7 4 4 7 7
Output Buffer Enable Delay[4]
[4]
Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time
1 1 1 7 2 1 5 5
1 1 1 8 2 1 6 6
Notes: 7. This parameter is measured with a positive-edge-triggered clock at the register. For the negative-edge clocking, the tACH and tACL parameter must be swapped.
5
CY7C344B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
C344B-11
External Synchronous tWH tWL
SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY
tSU
tH
tCO1
REGISTERED OUTPUTS
C344B-12
External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT
C344B-13
tAH
tAWH
tAWL
Internal Synchronous
CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE
C344B-14
tRD
tOD
6
CY7C344B
Switching Waveforms (continued)
Internal Combinatorial
tIN INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT
LOGIC ARRAY OUTPUT
tCOMB
OUTPUT PIN
tOD
C344B-15
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB
C344B-16
tAWH
tAWL
tF
tIC
tRSU
tRH
tFD
tCLR,tPRE
tFD
7
CY7C344B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CL OCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY
C344B-17
tICS
tRSU
tRH
Ordering Information
Speed (ns) 15 Ordering Code CY7C344B-15HC/HI CY7C344B-15JC/JI CY7C344B-15PC/PI CY7C344B-15WC/WI 20 CY7C344B-20HC/HI CY7C344B-20JC/JI CY7C344B-20PC/PI CY7C344B-20WC/WI 25 CY7C344B-25HC/HI CY7C344B-25JC/JI CY7C344B-25PC/PI Document #: 38-00860 Package Name H64 J64 P21 W22 H64 J64 P21 W22 H64 J64 P21 Package Type 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP Commercial/Industrial Commercial/Industrial Operating Range Commercial/Industrial
8
CY7C344B
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
51-80077
9
CY7C344B
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
10
CY7C344B
Package Diagrams (continued)
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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